In the fields of signal sampling and other high frequency applications, timing signals of up to 10 GHz or more are often used to control switches or other circuit elements. In such applications, it is generally desirable to avoid any skew, in other words timing mismatch, between the timing signals, which can result in the addition of unacceptable spurs.
One example is sampling circuitry, such as track and hold circuits, of a time-interleaved analog to digital converter (ADC). In such an ADC, a number of ADC cores are arranged in parallel, each having an input coupled to a corresponding track and hold circuit controlled by a clock signal to store an input signal at a given time instant. The clock signal of each track and hold circuit is offset with respect to the others such that the overall sampling rate applied to the input signal is higher than that of each clock signal.
In some applications the presence of skew between clock signals can be detected and corrected by feedback circuitry.
However, a problem with existing solutions for correcting skew is that they tend to add noise in the form of jitter to the clock signal, which is undesirable. There is thus a need in the art for a solution without such a problem.